up/down counter

날짜 : 04.12

제목 : up/down counter

module counter_up_down(
    input up_down_clk,
    input down,
    input reset,
    output reg [3:0] BCD_1=0,
    output reg [3:0] BCD_10=0,    
    output reg dec_clk=0
    );
    
    always @ (posedge up_down_clk or posedge reset) begin
        if(reset) begin
            BCD_1 <= 0;
            BCD_10 <= 0;
        end
        else begin 
            if(down) begin
                if(!BCD_1) begin
                    BCD_1 <= 9;
                    if(!BCD_10) begin
                        BCD_10 <= 5;
                        dec_clk <= 1;
                    end
                    else BCD_10 = BCD_10 - 1;
                end
                else begin 
                    BCD_1 <= BCD_1 - 1;
                    dec_clk <= 0;
                end   
            end
            else begin
                if(BCD_1 == 9) begin
                    BCD_1 <= 0;
                    if(BCD_10 == 5)  BCD_10 <= 0;
                    else BCD_10 <= BCD_10 + 1;
                end
                else BCD_1 <= BCD_1 + 1;
            end
        end
    end 
endmodule