FPGA

cook timer - 구조적 모델링

박순창 2021. 4. 13. 10:33
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날짜 : 0413

제목 : cook timer - 구조적 모델링

module cook_timer_struct(
    input clk,
    input [3:0] btn,
    output [3:0] led,
    output [3:0] com,
    output [6:0] seg_7
    );
    wire [3:0] debouced_btn;
    wire clk_msec, clk_sec, dec_clk;
    wire [3:0] hex_value;
    wire countdown_enable, countdown_enable_bar;
    wire [3:0] sec_1, sec_10, min_1, min_10;
    wire sec_up_clk, sec_down_clk, sec_up_down_clk;
    wire min_up_clk, min_down_clk, min_up_down_clk;
    wire debouced_btn3_bar;
    
    D_flip_flop D0 (.clk(clk_msec), .D(btn[0]), .Q(debouced_btn[0]), .reset(1'b1), .preset(1'b1));
    D_flip_flop D1 (.clk(clk_msec), .D(btn[1]), .Q(debouced_btn[1]), .reset(1'b1), .preset(1'b1));
    D_flip_flop D2 (.clk(clk_msec), .D(btn[2]), .Q(debouced_btn[2]), .reset(1'b1), .preset(1'b1));
    D_flip_flop D3 (.clk(clk_msec), .D(btn[3]), .Q(debouced_btn[3]), .reset(1'b1), .preset(1'b1));
    
    clock_10min G (.clk(clk), .clk_10min(clk_10min), .clk_sec(clk_sec), .clk_usec(clk_usec), .clk_msec(clk_msec));
    
    decoder_7seg D (.hex_value(hex_value), .seg_7(seg_7));
    
    seg7_switcher S (.clk_msec(clk_msec),
        .hex_value_1(sec_1), .hex_value_10(sec_10), 
        .hex_value_100(min_1), .hex_value_1000(min_10),
        .hex_value(hex_value), .com(com));
        
    not(debouced_btn3_bar, debouced_btn[3]);
    T_flip_flop T (.T(1'b1), .clk(debouced_btn[2]), .reset(debouced_btn3_bar), .Q(countdown_enable));
                                          
    not (countdown_enable_bar, countdown_enable);
    and (sec_up_clk, countdown_enable_bar, debouced_btn[0]);
    and (sec_down_clk, countdown_enable, clk_sec);     
    or (sec_up_down_clk, sec_up_clk, sec_down_clk);
                           
    counter_up_down UDsec (.up_down_clk(sec_up_down_clk), .down(countdown_enable), 
                           .BCD_1(sec_1), .BCD_10(sec_10), 
                           .reset(debouced_btn[3]), .dec_clk(dec_clk));
     
    and (min_up_clk, countdown_enable_bar, debouced_btn[1]);
    and (min_down_clk, countdown_enable, dec_clk);     
    or (min_up_down_clk, min_up_clk, min_down_clk);            
                  
    counter_up_down UDmin (.up_down_clk(min_up_down_clk), .down(countdown_enable), 
                           .BCD_1(min_1), .BCD_10(min_10),
                          .reset(debouced_btn[3]));                    
endmodule

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