stopwatch

날짜 : 21.04.14

제목 : FPGA stopwatch

장비 : zybo (digilent사), vivado(프로그램)

목표 : FND에 스탑워치 기능 구현

 

 

<>

module lap_time_switch(
    input [3:0] sec10,
    input [3:0] sec1,
    input [3:0] csec10,
    input [3:0] csec1,
    input clk, 
    input reset,
    input select_en,
    output reg [3:0]  ocsec_1,
    output reg [3:0]  ocsec_10,
    output reg [3:0]  osec_1,
    output reg [3:0]  osec_10
    );
    reg [3:0] s1,s10,cs1,cs10;
    
    initial begin
    
    end
    
    always @ (posedge clk or posedge reset) begin      
        if(reset) begin
            ocsec_1 <= 0;
            ocsec_10 <= 0;
            osec_1 <= 0;
            osec_10 <= 0;
        end
        else begin
          if(select_en) begin
            osec_10 = sec10;
            osec_1 = sec1;
            ocsec_10 = csec10;
            ocsec_1 = csec1;
            
            s1 = sec1;
            s10 = sec10;
            cs1 = csec1;
            cs10 = csec10;            
          end
          else begin
             osec_10 = s10;
            osec_1 = s1;
            ocsec_10 = csec10;
            ocsec_1 = csec1;
          end          
        end       
    end   
endmodule

날짜 : 04.14

장비 : zybo

프로그램 : vivado

module stop_watch(
    input clk,
    input [3:0] btn,
    output [3:0] com,
    output [6:0] seg_7
    );
    wire [3:0] debouced_btn;
    wire clk_msec, clk_sec, dec_clk;
    wire [3:0] hex_value;
    wire countdown_enable, select_en;
    wire [3:0] sec_1, sec_10, min_1, min_10;
    wire [3:0] ocsec_1, ocsec_10, osec_1, osec_10;
    wire sec_up_clk, sec_down_clk, sec_up_down_clk;
    wire min_up_clk, min_down_clk, min_up_down_clk;
    wire debouced_btn3_bar;
    
    D_flip_flop D0 (.clk(clk_msec), .D(btn[0]), .Q(debouced_btn[0]), .reset(1'b1), .preset(1'b1));
    D_flip_flop D1 (.clk(clk_msec), .D(btn[1]), .Q(debouced_btn[1]), .reset(1'b1), .preset(1'b1));
    D_flip_flop D2 (.clk(clk_msec), .D(btn[2]), .Q(debouced_btn[2]), .reset(1'b1), .preset(1'b1));
    D_flip_flop D3 (.clk(clk_msec), .D(btn[3]), .Q(debouced_btn[3]), .reset(1'b1), .preset(1'b1));
    
    clock_10min G (.clk(clk), .clk_sec(clk_sec), .clk_csec(clk_csec), .clk_msec(clk_msec));
    
    decoder_7seg D (.hex_value(hex_value), .seg_7(seg_7));
    
    seg7_switcher S (.clk_msec(clk_msec),
        .hex_value_1(ocsec_1), .hex_value_10(ocsec_10), 
        .hex_value_100(osec_1), .hex_value_1000(osec_10),
        .hex_value(hex_value), .com(com));
    
                                          
    not(debouced_btn3_bar, debouced_btn[3]);
    T_flip_flop T (.T(1'b1), .clk(debouced_btn[0]), .reset(debouced_btn3_bar), .Q(countdown_enable));
                                          
    and(csec_en ,clk_csec, countdown_enable);                       
    time_change Ucs (.up_clk(csec_en), .BCD_1(sec_1), .BCD_10(sec_10), .reset(debouced_btn[3]), .en(countdown_enable));
     
    and(sec_en ,clk_sec, countdown_enable);                            
    time_change_sec Us (.up_clk(sec_en), .BCD_1(min_1), .BCD_10(min_10), .reset(debouced_btn[3]), .en(countdown_enable));
    
    
    
    T_flip_flop T1 (.T(1'b1), .clk(debouced_btn[2]), .reset(debouced_btn3_bar), .Q(select_en));
    not(select_en_bar,select_en);
    and (in_sel, select_en_bar,clk_csec);
    
    lap_time_switch lts (.clk(in_sel), .reset(debouced_btn[3]), .select_en(select_en_bar),
                         .csec1(sec_1), .csec10(sec_10), .sec1(min_1), .sec10(min_10),
                         .ocsec_1(ocsec_1), .ocsec_10(ocsec_10), .osec_1(osec_1), .osec_10(osec_10));
endmodule

module time_change(
    input up_clk,
    input reset,
    input en,
    output reg [3:0] BCD_1=0,
    output reg [3:0] BCD_10=0,    
    output reg dec_clk=0
    );
    
    always @ (posedge up_clk or posedge reset) begin
        if(reset) begin
            BCD_1 <= 0;
            BCD_10 <= 0;
        end
        else begin
            if(en) begin 
            if(BCD_1 == 9) begin
                    BCD_1 = 0;
                    if(BCD_10 == 9)  BCD_10 = 0;
                    else BCD_10 = BCD_10 + 1;
                end
                else BCD_1 = BCD_1 + 1;
            end
            end
        end                                    
endmodule

module time_change_sec(
    input up_clk,
    input reset,
    input en,
    output reg [3:0] BCD_1=0,
    output reg [3:0] BCD_10=0,    
    output reg dec_clk=0
    );
    
    always @ (posedge up_clk or posedge reset) begin
        if(reset) begin
            BCD_1 <= 0;
            BCD_10 <= 0;
        end
        else begin 
            if(en) begin
            if(BCD_1 == 9) begin
                    BCD_1 = 0;
                    if(BCD_10 == 5)  BCD_10 = 0;
                    else BCD_10 = BCD_10 + 1;
                end
                else BCD_1 = BCD_1 + 1;
            end
            end
        end
endmodule