박순창

날짜 : 04.15 활동: 가변저항을 사용하여 xadc에서 나오는 값을 fnd 에 출력

날짜 : 21.04.14 제목 : FPGA stopwatch 장비 : zybo (digilent사), vivado(프로그램) 목표 : FND에 스탑워치 기능 구현 module lap_time_switch( input [3:0] sec10, input [3:0] sec1, input [3:0] csec10, input [3:0] csec1, input clk, input reset, input select_en, output reg [3:0] ocsec_1, output reg [3:0] ocsec_10, output reg [3:0] osec_1, output reg [3:0] osec_10 ); reg [3:0] s1,s10,cs1,cs10; initial begin end always @ (posed..

날짜 : 0413 제목 : cook timer - 구조적 모델링 module cook_timer_struct( input clk, input [3:0] btn, output [3:0] led, output [3:0] com, output [6:0] seg_7 ); wire [3:0] debouced_btn; wire clk_msec, clk_sec, dec_clk; wire [3:0] hex_value; wire countdown_enable, countdown_enable_bar; wire [3:0] sec_1, sec_10, min_1, min_10; wire sec_up_clk, sec_down_clk, sec_up_down_clk; wire min_up_clk, min_down_clk, min_u..

날짜 : 04.12 제목 : up/down counter module counter_up_down( input up_down_clk, input down, input reset, output reg [3:0] BCD_1=0, output reg [3:0] BCD_10=0, output reg dec_clk=0 ); always @ (posedge up_down_clk or posedge reset) begin if(reset) begin BCD_1

날짜 : 21.04.12 제목 : cook timer - 동작적 모델링 module cook_timer( input clk, input [3:0] btn, output [3:0] led, output [3:0] com, output [6:0] seg_7 ); wire [3:0] debouced_btn; wire clk_msec, clk_sec; reg [3:0] user_sec_1=0, user_sec_10=0; reg [3:0] user_min_1=0, user_min_10=0; wire [3:0] hex_value; reg [3:0] countdown_enable=0; reg [3:0] sec_1, sec_10, min_1, min_10; reg [3:0] hex_value_1, hex_value_1..

장비 : zybo 회사 : digilent 프로그램: vivado, vitis